Whenever multiple, parallel data streams clocked at a first lower rate are to be temporally multiplexed into one or more serial data streams of a higher rate, or whenever multiple data streams at some rate need to be available with a well-defined temporal phase relationship (e.g., before entering a digital-to-analog converter), it is important to temporally align the multiple, lower-rate, data streams. Often, the multiple data streams are generated inside an integrated circuit (IC), such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The generation of the lower speed parallel data streams within an IC, i.e., in the IC “fabric” or “core,” will typically be clocked in accordance with an internal clock of correspondingly lower frequency (RIC). The multiple, lower speed parallel data streams are provided by the IC fabric to corresponding high-speed transmitters of the IC for high-speed (RIO) serial output to external circuitry. While the transmitters of an IC are typically synchronized with each other on a time scale corresponding to RIC, they are not necessarily synchronized with each other on the much finer time scale corresponding to RIO.
The serialization carried out at each transmitter of the IC is typically at a substantially higher clock rate (e.g., RIO=10 GHz) than is available in the IC core (e.g., RIC=250 MHz). Each port will typically include circuitry to generate the higher rate clock based on the lower-rate core clock distributed to all ports by the core. As such, the different ports will have their own high speed clocks which will have the same frequency, but will not necessarily be in phase. In fact, the phase relationship among the various high speed clocks will generally be random and can change whenever the IC is powered up or re-programmed (in the case of an FPGA). This is due to the fact that the system and signal characteristics at the IC core clock frequency RIC are low-speed relative to RIO; in particular, signal rise times, pulse shapes, and device switching thresholds are representative of signals at RIC rather than of signals at RIO. As a result, using a low-speed, low-bandwidth clock signal, it is difficult to reliably synchronize multiple high-speed signals at RIO.
FIG. 1 illustrates the nature of the problem described above. FIG. 1 shows a portion of a cycle of the low-rate internal IC clock signal 10 (at RIC) with a region of uncertainty 10a within which the clock signal may fall. The synchronization of the high-rate RIO clock to the low-rate RIC clock will depend on the crossing of the low-rate clock through some threshold 12. The threshold 12 will also have a region of uncertainty 12a surrounding it. The overlap of the uncertainty regions 10a and 12a delimits a temporal range of uncertainty 20 over which the synchronization can occur. The range of uncertainty 20 may span several cycles of the high-speed IO clock signal (RIO), shown in FIG. 1 as signal 25, thus leading to misalignments of several bits.
As a result, data streams may be output by the IC with substantial temporal skew, or “inter-bit shift” amongst them. Instead of transitioning from one state to another synchronously, i.e., in “alignment,” the data streams will typically transition at different times and are said to be “misaligned.”
A solution to this alignment problem has been the use of parallel interface alignment protocols such as SFI-4 or SFI-5. This, however, requires that the device that receives the parallel data streams (e.g., a TDM multiplexer) is also equipped with such an interface, which may not always be the case in practice, and which may even be technically impossible.